T
he caching invalidation guidelines from the AMD-Vi specification (48882—Rev 3.07-PUB—Oct 2022) is incorrect on some hardware, as devices will malfunction (see stale DMA mappings) if some fields of the DTE are updated but the IOMMU TLB is not flushed. Such stale DMA mappings can point to memory ranges not owned by the guest, thus allowing access to unindented memory regions.
References
| Link | Resource |
|---|---|
| https://xenbits.xenproject.org/xsa/advisory-442.html | Vendor Advisory |
| http://xenbits.xen.org/xsa/advisory-442.html | |
| https://xenbits.xenproject.org/xsa/advisory-442.html | Vendor Advisory |
Configurations
History
04 Nov 2025, 20:16
| Type | Values Removed | Values Added |
|---|---|---|
| References |
|
18 Jun 2025, 16:15
| Type | Values Removed | Values Added |
|---|---|---|
| CWE | CWE-672 |
21 Nov 2024, 08:07
| Type | Values Removed | Values Added |
|---|---|---|
| References | () https://xenbits.xenproject.org/xsa/advisory-442.html - Vendor Advisory |
Information
Published : 2024-01-05 17:15
Updated : 2025-11-04 20:16
NVD link : CVE-2023-34326
Mitre link : CVE-2023-34326
CVE.ORG link : CVE-2023-34326
JSON object : View
CWE